The present invention relates to a phase-locked loop (PLL), and more particularly, to a loop gain compensation scheme for a controllable oscillator in a PLL, and a method thereof.
FIG. 1 is a related art phase locked loop (PLL) 100. The PLL 100 includes a phase/frequency detector 111, a charge pump circuit 112, a loop filter 113, a voltage-controlled oscillator (VCO) 114, a frequency divider 115 and a modulating device 12. The PFD 111 is arranged to receive a reference signal Fref and a feedback signal Ffb, and output a pulse signal according to a comparison result of the feedback signal Ffb and the reference signal Fref. The charge pump circuit 112 is arranged to convert the pulse signal into an error current. The loop filter 113 is arranged to integrate the error current to generate a control voltage. The VCO 114 is arranged to receive the control voltage from the loop filter 113 and generate an oscillating signal FVCO according to the control voltage. The frequency divider 115 is arranged to generate the feedback signal Ffb according to the oscillating signal received from the VCO 114.
For simplicity in loop gain calibration, a type I PLL based transmitter is usually applied in communication systems, e.g. the loop filter 113 shown in FIG. 1 is a type I PLL. The type I PLL cannot track the temperature ramping, however, thus causing frequency errors when the temperature changes.
Therefore, there is a need for a novel method and an associated apparatus to solve the above issue.